1. Technical Field
The present invention relates to a delay circuit, and an oscillator circuit and a semiconductor device each including the delay circuit.
2. Background Art
A related-art delay circuit is now described. FIG. 4 is a circuit diagram for illustrating the related-art delay circuit.
The related-art delay circuit includes inverters 611, 617, and 618, an NMOS transistor 612, PMOS transistors 615 and 616, a capacitor 613, a constant current circuit 614, an input terminal VIN, an output terminal VOUT, a power supply terminal 101, and a ground terminal 100.
FIG. 5 is a timing chart for illustrating operation of the related-art delay circuit.
After a power supply voltage VDD of the power supply terminal 101 is raised, when a voltage of the input terminal VIN is Low, a voltage of a node 631 becomes High to turn on the NMOS transistor 612 and turn off the PMOS transistor 616. The capacitor 613 is discharged due to the NMOS transistor 612 being turned on, and a node 632 becomes Low. At this time, because an inverted output of the inverter 617 is High, a voltage of a node 633 becomes High. Accordingly, the PMOS transistor 615 is turned off and a voltage of the output terminal VOUT becomes Low.
When the voltage of the input terminal VIN is changed to High, the voltage of the node 631 becomes Low to turn off the NMOS transistor 612 and turn on the PMOS transistor 616. The capacitor 613 starts to be charged when the NMOS transistor 612 is turned off, and hence the voltage of the node 632 is increased. Then, when the voltage of the node 632 exceeds a detection voltage VR1 of the inverter 617, the voltage of the node 633 becomes Low to turn on the PMOS transistor 615, and the voltage of the output terminal VOUT is changed to High. In this way, a time (Td) from a time point at which the voltage of the input terminal VIN is changed from Low to High to when the voltage of the node 632 exceeds the detection voltage VR1 is delayed, to thereby change the voltage of the output terminal VOUT from Low to High (for example, see Patent Literature 1).